Why is the scaling speed of SRAM slower than logic?

The scaling of SRAM lags behind logical scaling, mainly due to the strict design rules in the latest technology. In the past, we had separate design rules for SRAM, which allowed us to reduce the size even more than logic transistor based designs. However, as we move towards smaller sized nodes, maintaining this distinction becomes increasingly challenging. Nowadays, SRAM is following more and more logic design rules, and compared to logic transistor based designs, the advantage of further reducing memory is not obvious.
 

In addition, the size of the memory is also important, as this design is repeated millions of times on the chip, thereby affecting the cost of the chip. However, when we migrate from lower technologies in recent years, the benefits have been diluted because we will ultimately spend more money migrating to lower technology nodes instead of the benefits of reducing SRAM memory size. This is the main challenge we face in our efforts to improve the SRAM density in AI chips.