​French company raises $11m for spin MRAM development

Antaios SA (Grenoble, France), a 2017 startup working on spin-orbit-torque (SOT) MRAM has secured US$11 million in funding.
 
The funding for the spin-orbit-torque (SOT) MRAM startup is led by French venture capital firms Innovacom and Sofimac Innovation, together with Applied Ventures LLC , the venture capital arm of chipmaking equipment supplier Applied Materials Inc. Additional financing also comes from Bpifrance (French public Investment Bank) and other bank partners.
 
Applied Materials, along with ARM Ltd., is a big backer of MRAM technology development having also invested considerable sums in Spin Memory Inc. (Fremont, Calif.).
 
SOT-MRAM represents a further development beyond spin-torque transfer (STT) MRAM. It holds out the possibility of the exceptional endurance cycling required to become the long-awaited universal embedded non-volatile memory.
   
"This funding is a key milestone for Antaios, asserting the value of our technology and the industry’s interest for SOT as the next-generation MRAM, which solves the limitations of its current implementations," said Jean-Pierre Nozières, CEO of Antaios, in a statement.
 
Michael Stewart, investment director at Appled Ventures, has joined the board of Antaios as observer. He said: "Applied Ventures supports the continued development of logic-based embedded memory technologies like MRAM that offer low power, high performance and high endurance for Internet of Things and edge AI devices."
 
By enabling simultaneously high operating speed and infinite read/write endurance, SOT has the potential to replace both embedded non-volatile memory and SRAM cache in microcontrollers, microprocessors and system-on-chip designs.
 
If SOT-MRAM could be used to replace SRAM in registers, flip-flops, scratch-pad memories very close to and within the logic circuits it could have a major impact on how processors are designed to operate. MRAM already has the advantage of non-volatility and density over SRAM memory cells, which typically use six transistors for implementation, but it needs to demonstrate exceptional endurance cycling to be applicable in logic.