​TSMC's Moore's Law has no problem evolving to 1 nanometer

As TSMC continues to promote advanced processes such as 7nm, 5nm, and 3nm, the industry's attention to it continues to increase. During the 2020 World Semiconductor Conference on August 26, Luo Zhenqiu, general manager of TSMC (Nanjing) Co., Ltd., introduced the company's planning and layout in advanced technology and 3D packaging technologies.
 
Luo Zhenqiu said that TSMC has divided the 7-nanometer node into 3 sub-nodes, including 7-nanometer, 7-nanometer enhanced version N7+ and 6-nanometer. At this node, TSMC’s chip output is very large, so far it has produced more than 1 billion chips, and its application areas include CPU, GPU, communication chips and AI.
 
At present, TSMC's 5nm has now entered the mass production stage. TSMC will still adopt a small-step fast-moving research and development model to continuously improve power consumption, performance, and area. The 5nm node will also plan 3 subdivision nodes, including 5nm, 5nm enhanced version N5+ and 4nm. According to Luo Zhenqiu's introduction, judging from the production of 5 nanometers, its yield rate is much better than that of 7 nanometers three years ago. 4nm is expected to begin mass production in 2021.
 
As the process continues to advance, some people in the industry are worried that Moore's Law will continue to go down? Luo Zhenqiu said that we have seen 3 nanometers, 2 nanometers, and 1 nanometers so far. TSMC's 3nm output performance can be increased by 10-15%, and power consumption can be reduced by 25-30%. It is expected that next year, 3nm products will enter mass production in 2022.
 
In terms of advanced packaging, Luo Zhenqiu believes that advanced packaging is the main driver for the continuous evolution of Moore's Law. TSMC divides 3D packaging into front-end 3D packaging and back-end 3D packaging. The front 3D packaging adopts SoIC technology, including CoW (Chip on Wafer packaging) and WoW (Wafer on Wafer) packaging; the back 3D packaging adopts InFO packaging and CoWoS packaging technology to integrate chips with different functions into a system-level product among. This is a very effective and lower cost method.