How to choose the most suitable SRAM memory
SRAM(static random access memory) is a kind of just under the condition of the power supply can store data storage devices, and is a key part of the most high performance systems.SRAM has many architecture, each about a specific application.This paper aims at the current existing SRAM for full review on the market, and a brief explanation for certain purposes, what kind of SRAM is the best choice.SRAM from high level can be divided into two broad categories: synchronous and asynchronous.Type synchronous SRAM made an input clock to start to the memory of all the transaction (reading, writing and deselect, etc.).The type asynchronous SRAM is does not have the clock input, and must monitor the input in order to get from the command of the controller.Once you identify one of the commands, these devices will be immediately executed.
Synchronous SRAM classification
Adapted to a particular application of the selection of the best SRAM depends on several factors, including the power limitation, bandwidth requirements, density, and the read/write operation mode, etc.Can meet the requirements of different systems of synchronous and asynchronous SRAM is varied, this paper will be one by one.
All kinds of synchronous type SRAM
Synchronous type SRAM in the market for the first time since the late 80 s of the last century, the original is an has a very high performance workstations and servers in the first level 2 (L2) cache memory.After the mid - 90 - s last century, the application of it in more mainstream (including secondary cache memory in the PC) found in their own place.After that, in many applications, including high performance network, in the design of synchronous type SRAM is popular (in these applications, they are often used in the data buffer, high-speed register, queue management functions and statistical buffer).
1: standard type synchronous SRAM
Standard type synchronous SRAM is received by the "mainstream" of the first type synchronous SRAM.Although these devices for main PC L2 cache memory applications, but also permeated the PC applications, such as network, telecommunications, digital signal processing (DSP) and medical and test equipment.Among them, the standard type synchronous SRAM has two basic formats: pipeline and straight type.The difference between the two is that the pass-through type SRAM only on the input register, when the address and control input is captured and a read access operation is started, the data will be allowed to "flow" directly to the output.When the user to consider more than the initial delay for constant bandwidth fastidious, people often preferred direct type architecture."Pipeline" synchronous SRAM has both an input and an output registers.Pipeline SRAM provides the working frequency and bandwidth is generally higher than straight-through type SRAM.As a result, the demand is higher broadband, and is sensitive to the initial delay is not, people often preferred pipeline SRAM.
Type 2: NoBLTM (no bus delay) SRAM
Some applications are not allowed to "waiting".Such as network application in the "waiting" may have a significant impact on performance.To solve this problem, the company launched plath bus delay (NoBL) SRAM.NoBL type SRAM and standard synchronization type SRAM are similar, but with additional on-chip logic circuit, is designed to eliminate synchronization standard type SRAM series "waiting" as needed.By eliminating the "waiting", this kind of SRAM can achieve 100 [%] bus utilization (not influenced by the read/write mode).The function greatly improve the storage performance, especially when there are frequent when they read/write operation change.
Type NoBL SRAM has two versions: direct type and pipeline.Straight-through type NoBL SRAM always has a single cycle, while keep NoBL pipeline SRAM by a double cycle shift.
3: four times the data rate (QDRTM) SRAM
Although introduced NoBL type structure type and synchronize the performance than the standard SRAM have improved, but some systems have a higher requirement for performance.So, plath, Renesas, IDT, NEC and samsung companies jointly developed a QDR SRAM.QDR architecture is designed to meet the requirements of low delay, and significantly higher than the bandwidth required NoBL type architecture provides the capability of the needs of the "high bandwidth XuQiuXing" system.Type QDR SRAM and NoBL SRAM read one of the most significant differences is the former port and port is separated.These ports can work independently, and supports concurrent read and write the transaction.Type QDR SRAM to DDR transmission rate (2 times) to support two simultaneous occurrence of transaction processing, data rate (QDR) name is four times as much as this.
QDR SRAM has two basic types: 2 pulse sequence and 4 words pulse sequence.The difference between the two types is that every transaction processing in the process of the pulse sequence length.
4: QDR - type II SRAM
QDR - II type SRAM and QDR SRAM are similar, but in terms of performance further ascension.Compared with the same frequency QDR type device, QDR - the total number of type II SRAM produced according to effective large window area around 35 [%].In addition, the QDR - II type than the QDR SRAM product type device for more than one and a half delay period.The increase of half a clock cycles can be in with minimal impact on the initial delay provide much higher frequency and bandwidth.
5: DDR SRAM
If type QDR SRAM is oriented with a balanced application of read/write mode, DDR type SRAM architecture is mainly aimed at the need for data streaming transmission (for example, with a number of write operations after a number of read operation), and the required bandwidth is much higher than standard NoBL type synchronous device or type of device applications.DDR type SRAM has a superior overall utilization rate of bus and much higher total bandwidth, thus obtained the maximum performance.
Type and type QDR SRAM, DDR SRAM has two formats: namely 2 pulse sequence and 4 words pulse sequence.What choose which kind of depends on the required data granularity and memory data bus width.
The second type an SRAM for asynchronous SRAM.Those who do not have the clock input of the SRAM is asynchronous.In these devices, read and write operations will be started immediately after the device receives the instruction.
Using asynchronous SRAM one of the biggest advantages is that they have for decades the use of history and has fully understand by people.Because type asynchronous SRAM has hit the market for a long time, many have been equipped with standard processors are included interface type asynchronous SRAM memory controller, so as to minimize the workload of the design.The typical type asynchronous SRAM access time is 8 ns (or longer).As a result, they generally applied to the clock frequency of 100 MHZ (or lower) in the system.Type asynchronous SRAM can be further divided into two main categories: namely fast asynchronous SRAM and low-power asynchronous SRAM (MoBLTM).
Type 1: fast asynchronous SRAM
Access time of 35 ns (or less) type asynchronous SRAM can be classified as a "quick" type asynchronous SRAM.These memory are often used in the old system, and higher power consumption (1/2 w or higher is commonplace).Its typical applications include the old PC L2 cache memory and high-speed buffer memory in the register, and industrial applications.
Type 2: MoBLTM low-power asynchronous SRAM
Some applications (such as mobile phones) focus on power is far more than the performance level of concern.Therefore, manufacturers (such as) plath company launched a very low power SRAM series.Sephora, MoBL (means longer battery life) low power type asynchronous SRAM product library collected many typical access time of about 40 ns (or more), and designed to achieve low power consumption and optimization of the device.Typical standby power consumption can be as low as 10 mu W (or lower), while the running power consumption can be as low as 30 mw (or lower).These devices of different storage density, from 64 KB to 16 MB.
Pseudo SRAM (i.e. PSRAM)
If you need more than 16 MB of storage density, the PSRAM (or pseudo PSRAM) is a kind of feasible solutions.Pseudo SRAM refers to a kind of has a DRAM memory kernel and a "type SRAM interface of storage devices.Because the PSRAM USES a DRAM kernel, and therefore the need for periodic refresh, in order to save the data.But the difference is that standard DRAM refresh control was conducted on the outside of the device, while PSRAM has an "implicit" refresh circuit, which makes them can be easily used in other type asynchronous SRAM memory density upgraded devices.
conclusion
When choosing an SRAM, you will face many options.In some cases, the choice is limited.Many processors has established himself as a solid contains support special SRAM memory controller architecture.The design of the new type of processor is more flexible.In order to determine the best alternative, crucial is to determine the storage subsystem (megabit per second, the initial delay, power consumption operation and standby power consumption and cost, etc.) of the priority and the work characteristics of the system (read/write mode, working frequency, etc.).
Network applications tend to be close to 50/50 of the read/write mode, it is suitable for using the QDR series solution.Other applications (and even within the same system function circuit) are often has the imbalance of the read/write mode, it is suitable for using common I/O architecture, including standard synchronization, NoBL and DDR type.
Some system requirements may be the lowest power consumption, so as to prolong the service life of the battery, the optional solution of an SRAM and PSRAM MoBL type respectively.
keywords:sram
Synchronous SRAM classification
Adapted to a particular application of the selection of the best SRAM depends on several factors, including the power limitation, bandwidth requirements, density, and the read/write operation mode, etc.Can meet the requirements of different systems of synchronous and asynchronous SRAM is varied, this paper will be one by one.
All kinds of synchronous type SRAM
Synchronous type SRAM in the market for the first time since the late 80 s of the last century, the original is an has a very high performance workstations and servers in the first level 2 (L2) cache memory.After the mid - 90 - s last century, the application of it in more mainstream (including secondary cache memory in the PC) found in their own place.After that, in many applications, including high performance network, in the design of synchronous type SRAM is popular (in these applications, they are often used in the data buffer, high-speed register, queue management functions and statistical buffer).
Synchronous type SRAM can use a variety of different architecture.Below will be of some of the "mainstream" devices do brief explanation.
1: standard type synchronous SRAM
Standard type synchronous SRAM is received by the "mainstream" of the first type synchronous SRAM.Although these devices for main PC L2 cache memory applications, but also permeated the PC applications, such as network, telecommunications, digital signal processing (DSP) and medical and test equipment.Among them, the standard type synchronous SRAM has two basic formats: pipeline and straight type.The difference between the two is that the pass-through type SRAM only on the input register, when the address and control input is captured and a read access operation is started, the data will be allowed to "flow" directly to the output.When the user to consider more than the initial delay for constant bandwidth fastidious, people often preferred direct type architecture."Pipeline" synchronous SRAM has both an input and an output registers.Pipeline SRAM provides the working frequency and bandwidth is generally higher than straight-through type SRAM.As a result, the demand is higher broadband, and is sensitive to the initial delay is not, people often preferred pipeline SRAM.
Type 2: NoBLTM (no bus delay) SRAM
Some applications are not allowed to "waiting".Such as network application in the "waiting" may have a significant impact on performance.To solve this problem, the company launched plath bus delay (NoBL) SRAM.NoBL type SRAM and standard synchronization type SRAM are similar, but with additional on-chip logic circuit, is designed to eliminate synchronization standard type SRAM series "waiting" as needed.By eliminating the "waiting", this kind of SRAM can achieve 100 [%] bus utilization (not influenced by the read/write mode).The function greatly improve the storage performance, especially when there are frequent when they read/write operation change.
Type NoBL SRAM has two versions: direct type and pipeline.Straight-through type NoBL SRAM always has a single cycle, while keep NoBL pipeline SRAM by a double cycle shift.
3: four times the data rate (QDRTM) SRAM
Although introduced NoBL type structure type and synchronize the performance than the standard SRAM have improved, but some systems have a higher requirement for performance.So, plath, Renesas, IDT, NEC and samsung companies jointly developed a QDR SRAM.QDR architecture is designed to meet the requirements of low delay, and significantly higher than the bandwidth required NoBL type architecture provides the capability of the needs of the "high bandwidth XuQiuXing" system.Type QDR SRAM and NoBL SRAM read one of the most significant differences is the former port and port is separated.These ports can work independently, and supports concurrent read and write the transaction.Type QDR SRAM to DDR transmission rate (2 times) to support two simultaneous occurrence of transaction processing, data rate (QDR) name is four times as much as this.
QDR SRAM has two basic types: 2 pulse sequence and 4 words pulse sequence.The difference between the two types is that every transaction processing in the process of the pulse sequence length.
4: QDR - type II SRAM
QDR - II type SRAM and QDR SRAM are similar, but in terms of performance further ascension.Compared with the same frequency QDR type device, QDR - the total number of type II SRAM produced according to effective large window area around 35 [%].In addition, the QDR - II type than the QDR SRAM product type device for more than one and a half delay period.The increase of half a clock cycles can be in with minimal impact on the initial delay provide much higher frequency and bandwidth.
5: DDR SRAM
If type QDR SRAM is oriented with a balanced application of read/write mode, DDR type SRAM architecture is mainly aimed at the need for data streaming transmission (for example, with a number of write operations after a number of read operation), and the required bandwidth is much higher than standard NoBL type synchronous device or type of device applications.DDR type SRAM has a superior overall utilization rate of bus and much higher total bandwidth, thus obtained the maximum performance.
Type and type QDR SRAM, DDR SRAM has two formats: namely 2 pulse sequence and 4 words pulse sequence.What choose which kind of depends on the required data granularity and memory data bus width.
Various type asynchronous SRAM
The second type an SRAM for asynchronous SRAM.Those who do not have the clock input of the SRAM is asynchronous.In these devices, read and write operations will be started immediately after the device receives the instruction.
Using asynchronous SRAM one of the biggest advantages is that they have for decades the use of history and has fully understand by people.Because type asynchronous SRAM has hit the market for a long time, many have been equipped with standard processors are included interface type asynchronous SRAM memory controller, so as to minimize the workload of the design.The typical type asynchronous SRAM access time is 8 ns (or longer).As a result, they generally applied to the clock frequency of 100 MHZ (or lower) in the system.Type asynchronous SRAM can be further divided into two main categories: namely fast asynchronous SRAM and low-power asynchronous SRAM (MoBLTM).
Type 1: fast asynchronous SRAM
Access time of 35 ns (or less) type asynchronous SRAM can be classified as a "quick" type asynchronous SRAM.These memory are often used in the old system, and higher power consumption (1/2 w or higher is commonplace).Its typical applications include the old PC L2 cache memory and high-speed buffer memory in the register, and industrial applications.
Type 2: MoBLTM low-power asynchronous SRAM
Some applications (such as mobile phones) focus on power is far more than the performance level of concern.Therefore, manufacturers (such as) plath company launched a very low power SRAM series.Sephora, MoBL (means longer battery life) low power type asynchronous SRAM product library collected many typical access time of about 40 ns (or more), and designed to achieve low power consumption and optimization of the device.Typical standby power consumption can be as low as 10 mu W (or lower), while the running power consumption can be as low as 30 mw (or lower).These devices of different storage density, from 64 KB to 16 MB.
Pseudo SRAM (i.e. PSRAM)
If you need more than 16 MB of storage density, the PSRAM (or pseudo PSRAM) is a kind of feasible solutions.Pseudo SRAM refers to a kind of has a DRAM memory kernel and a "type SRAM interface of storage devices.Because the PSRAM USES a DRAM kernel, and therefore the need for periodic refresh, in order to save the data.But the difference is that standard DRAM refresh control was conducted on the outside of the device, while PSRAM has an "implicit" refresh circuit, which makes them can be easily used in other type asynchronous SRAM memory density upgraded devices.
conclusion
When choosing an SRAM, you will face many options.In some cases, the choice is limited.Many processors has established himself as a solid contains support special SRAM memory controller architecture.The design of the new type of processor is more flexible.In order to determine the best alternative, crucial is to determine the storage subsystem (megabit per second, the initial delay, power consumption operation and standby power consumption and cost, etc.) of the priority and the work characteristics of the system (read/write mode, working frequency, etc.).
Network applications tend to be close to 50/50 of the read/write mode, it is suitable for using the QDR series solution.Other applications (and even within the same system function circuit) are often has the imbalance of the read/write mode, it is suitable for using common I/O architecture, including standard synchronization, NoBL and DDR type.
Some system requirements may be the lowest power consumption, so as to prolong the service life of the battery, the optional solution of an SRAM and PSRAM MoBL type respectively.
keywords:sram
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