Dual port sram characteristics is introduced

　　

If access to the same storage cell of dual port RAM at the same time, will cause the distortion of data access.In order to prevent the happening of the conflict, the Busy logic control, also known as hardware address arbitration logic.Here the address bus is given only to choose communication signals prior to slice the pulse signal.

And, at the ends of the selected signal at least vary tAPS - arbitration minimum time interval (IDT7132 for 5 ns), internal arbitration logic control to give access to one output is Busy locking signals, after the access to the other side until the end of the location of access, to undo the Busy blocking signal, the access to the other side until the end of the location of access, to undo the Busy blocking signal.

Even in extreme conditions, the two CPU access almost at the same time the same unit, address matching pieces selected signal low jump is less than the difference between the tAPS and Busy blocking signal is output only to either the CPU, only allow a CPU unit to access the address.Arbitration control not Busy to two cpus, blocking signals at the same time.

(2) of the storage unit block access rights allocation

Access storage unit block distribution is only allowed in a certain time period by a CPU to the custom of a block of data read and write operations, this will help to store data protection, avoid address conflict more effectively.Semaphores (Semaphore, referred to as SEM) arbitration atresia is a kind of hardware circuit method combining software realization access allocation.SEM unit are symbols of the independence has nothing to do with the storage unit unit, figure 3 shows a semaphore atresia logic diagram.

Both trigger during initialization makes SEM to allow output to high level, waiting for the application of SEM.If received a written by SEM signal (usually low level writing), as shown in figure 3, the arbitration will make one of the trigger circuit of SEM to allow output to low level, and blocking another SEM allows the output to make it continue to maintain a high level.

Only should ask the party to withdraw SEM signal, namely writing high level, to make another SEM allows the output atresia lifted and restore waiting for new application for SEM.

(3) signal switching logic (signaling logic)

In order to improve the exchange capacity of data, some of the dual port RAM signal switching logic is used to notify the other party.IDT7130 capacity (1 k) is the interrupt mode switching signal.Using two special units (FFH 3 and 3 feh) as signaling words and interrupt source.Assume that the left CPU to write signaling, 3 FFH will be triggered by signals and address gating signal interruption of the right output, only when the right CPU interrupt response and reads the FFH signaling unit 3, which was a dual port RAM removal.

 

 

Key words:sram