MRAM pioneer develops 20nm magnetic tunnel

 

MRAM technology developer Spin Transfer Technologies (STT) has developed magnetic tunnel junctions down to 20nm in width.

 

The company is a subsidiary of Allied Minds LLC, essentially the method by which Allied Minds acts as an investor in the start-up. Barry Hoberman, CEO of STT, told EE Times Europe that the use of a back-end of line (BEOL) R&D fab built by the company at its base in California has been the key to getting a series of devices made and characterised in a timely manner.

 

STT has been pioneering something called orthogonal spin transfer (OST) MRAM in which the magnetic fields of the pinned and variable magnetic layers are perpendicular to the plane of the surface of the wafer. One of STT's developments is to put an additional spin polarising filter above the variable magnetic field layer.

Figure 1: An additional spin polarisation filter and proprietary write and read circuitry contribute to claimed advantages for OST-MRAM. (Source: Spin Transfer Technologies)

 

The R&D fab has allowed the company to compress engineering development cycles to 10 days that otherwise would have taken several months, said Hoberman, CEO of STT. “In just four years, STT has taken the journey from incubation to commercialization. We are excited to enter the next phase of the company’s evolution," he said in a statement.

 

MRAM is also being investigated elsewhere and is now being tipped as the prime embedded non-volatile memory option at 28nm.

 

ST-MRAM beats DRAM, SRAM for cache in many applications and is superior to embedded flash at 28nm and below where it demonstrates 1000x lower write energy and can be implemented in BEOL for easy integration with analog, high-voltage and RF. Resistive RAM (ReRAM) alternatives have yet to demonstrate reliability.

 

Since 2012, STT has raised $106 million in venture capital—$36 million early in 2012 and $70 million in October 2014.

 

Hoberman said STT's business model is two-fold; to be a fabless supplier of stand-alone MRAMs under its own brand and to act as a technology licensor to put the technology into SoCs as embedded memory by licensing to the fabless/foundry ecosystem and to IDMs.

 

"We have working devices on hand and feel we are in a position to get the best trade off of speed, power and endurance at the device level. We are not announcing sampling yet but we have initiated the sampling program," Hoberman said. "We have working samples and we have had requests for samples. We are evaluating those requests."

 

He made the point that STT needs to focus on working with and supporting just a few companies that are committed to bringing the technology to market.

 

Almost all companies that are working in the MRAM sector are pursuing perpendicular architecture but that STT has additional technology and circuitry that provides an advantage in terms of deterministic write onset and short write pulses. One drawback of MRAM is that it demonstrates some probabilistic behavior down the parts per billion level, said Hoberbman. "Reliable memory requires extra circuitry and extra margins," he said.

 

With regards to the sampling he said: "We are not in product mode. We are in technology demo mode." For this reason the sample would include an MRAM array at a smaller size than 1Mbit and a companion multi-megabit circuit. And for cycling endurance he said STT's MRAMs had "sailed past" the 10^6 cycles that is a limit for embedded flash. "We think 10^9 to 10^14 is within reach," he said.

 

The STT MTJ also has voltage regime that reads at voltages of 100 to 150mV and writes at voltages of the order of 700mV.

 

Hoberman declined to disclose details of the magnetic layers used in the company's memory. "There are probably 20 elements from the periodic table and all the usual suspects, magnesium oxide, stoichiometric mixes of cobalt, iron, boron. But there are 30 to 60 layers. The secret sauce is ordering and construction of those layers," he said.

 

The company is currently preparing evaluation boards to enable customers to fully evaluate the parameters of the memory.

Keywords：sram    memory